DR. John Nguyen
SUMMARY:
- More than twenty years of experience as an ASIC/FPGA design and verification engineer working with Computer Interface Protocols, Digital Signal Processing, and digital communication applications.
- Job experience in micro architecture design, RTL coding, synthesis, static timing analysis, and PNR.
- Job experience in chip simulation and verification using Verilog, ModelSim, and Matlab
- Highly motivated, creative, team player, with excellent interpersonal skills.
- Hard working, reliable, committed to professionalism, and able to multi-task effectively
- Excellent analytical and problem-solving skills.
- Have delivered five successful products.
- Worked on PCI and PCIe interface
- Worked on SRAM, DRAM, SDRAM, and DDR2 Memory interface.
- Đã hoạt động trên NAND, FLASH và MRAM
- Worked on NAND, FLASH, and MRAM interface.
- Experienced with Xilinx Spartan family
- Integrating Matlab with ModelSim to simulate BER performance in digital communication
receiver.
- Worked with System Architect to convert Matlab conceptual design to hardware implementation achieving the speed performance.
PROFESSIONAL EXPERIENCE:
FPGA Design Engineer
Analog Inference, Inc., Santa Clara, CA
July 2021– Present
- Designed and implemented memory controllers.
- Designed and implemented FPGA test platform.
- System verification of the embedded memory module.
- Wrote behavioral Verilog models for customers.
MTS Design Engineer
Crossbar, Inc., Santa Clara, CA
Nov 2014 – July 2021
- • Designed and implemented RRAM controllers.
- Designed and implemented FPGA test platform for the RRAM.
- Physical Designed using Cadence Encounter 14.1.
- System verification of the RRAM embedded environment.
- Wrote behavioral Verilog models for customers.
Sr. ASIC Design Engineer
Crocus Technology, Inc., Santa Clara, CA
Jan 2013 – Nov 2014
- Designed and implemented the MRAM demo board.
- Designed and implemented the MLU-MiP test boards
- Thiết kế và triển khai 1 demo Box với Android
- Thiết kế và xác thực với thẻ thông minh ISO7816
- Designed and implemented a demo box with an Android OS.
- Designed and verified an ISO7816 smartcard IP.
- FPGA platform debug using Chipscope Pro.
Sr. FPGA Design Engineer
SanDisk Corp., Milpitas, CA
Jan 2012 – Dec 2012
- Thiết kế và triển khai giao thức bus NAND
- Thiết kế và triển khai với ATBU
- Thiết kế và xác minh với các chuẩn USB2, SRAM, và DDR2
- Thiết kế và xác minh RTL
- Tổng hợp Chip và phân tích thời gian
- Mô phỏng và xác thực sử dụng ModelSim và Chipscope.
- Thực hiện địa điểm & tuyến đường trên dòng FPGA Xilinx Spartan bằng Xilinx ISE xx
- Mã hóa các mô-đun kiểm tra hành vi để mô phỏng và xác thực
Kỹ sư FPGA Design Engineer
AAE Systems Inc., Sunnyvale, CA
Dec 2002 – Nov 2011
- Implemented and verified a CPFSK modem with a Viterbi Algorithm.
- Micro architecture design and RTL coding.
- Coding behavioral module for simulation and verification.
- Running chip synthesis and timing analysis.
- System simulation and verification using ModelSim SE and Matlab.
- Performed place & route on Xilinx Spartan 3 & 6 FPGAs using Xilinx ISE 13.1.
- Converting System Architect’s Matlab conceptual design into FPGA implementable RTL code achieving the timing and size requirements.
FPGA Design Engineer
ComTier Inc., Sunnyvale, CA
Apr 2001 – Sept 2002
- Micro architecture design and RTL coding
- Logic design, RTL coding, synthesis, and timing analysis.
- Writing and maintaining synthesis scripts.
- Integrating and verifying sub-modules and whole chip design.
- Block and whole chip debugging and verification.
- Coding behavioral modules for system testing.
- Writing test-benches using C, Matlab and Perl script.
ASIC Design Engineer
Advanced Micro Devices, Sunnyvale, CA
Jun 1999 – Apr 2001
- Logic design, Behavior RTL coding, synthesis, and timing analysis.
- Writing and maintaining synthesis scripts.
- Integrating and verifying sub-modules and whole chip design.
- Block and whole chip debugging and verification.
- Coding behavioral modules for system testing.
- Writing testbenches using C, Matlab and Perl script.
EDUCATION:
Bachelor of Science in Electrical Engineering – 1998
Minor in Computer Science
Sacramento State University
Synopsys Education and Training Services:
- Basic Verilog with VCS Workshop
- Chip Synthesis Workshop
- Advanced Verilog Workshop
- VERA Workshop
- Verilog Coding Styles for RTL Synthesis Workshop
- Module Compiler Workshop
REFERENCES: Available upon request.
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